This invention relates to integrated circuit fabrication, and more specifically to the formation of electrical contacts and vias through insulating dielectric layers.
Integrated circuits typically include a silicon substrate covered by a dielectric insulating layer such as silicon dioxide. On top of the silicon dioxide are conductive traces. At selected areas, holes are formed in the silicon dioxide and the conductive traces are permitted to make electrical contact with devices (e.g., transistors, diodes and resistors) formed within the silicon substrate. A contact during various stages of a prior art fabrication process is illustrated in FIGS. 1a through 1e. (As used in this patent, the term "contact" means a hole in an insulating material which permits an electrically conductive material to be electrically connected to a semiconductor substrate.) FIG. 1a illustrates a cross section of a silicon wafer 1 coated with a silicon dioxide layer 2. Silicon dioxide layer 2 is provided through any of a variety of means such as chemical vapor deposition (CVD) or thermal oxidation. Above silicon dioxide layer 2 is a photoresist layer 3. Photoresist layer 3 is then selectively exposed to light, and the portions of photoresist layer 3 exposed to light are then removed, thereby forming a window 4 in photoresist layer 3, as shown in FIG. 1b.
After forming window 4 in photoresist layer 3, the wafer is then subjected to a reactive ion etch (RIE) process. This process is typically accomplished at a pressure of approximately 20 to 80 millitorr using a gas mixture which is approximately 30 to 40% oxygen and 70 to 60% CHF.sub.3 and a power in the range of 1000 to 1200 watts. The RIE process attacks both photoresist layer 3 and silicon dioxide layer 2. This continues until a profile such as the one illustrated in FIG. 1c is achieved, at which time the oxygen is substantially removed from the plasma and the RIE process is continued until the profile illustrated in FIG. 1d is achieved. (As is explained below, the oxygen is removed to prevent etching of silicon wafer 1.) Thereafter, photoresist layer 3 is removed and, as shown in FIG. 1e, metal layer 5 is deposited upon silicon wafer 1 using any of a variety of known processes, e.g. sputtering.
When using a reactive ion etch in the presence of significant amounts of oxygen, edge 3a (FIG. 1c) of photoresist layer 3 is eroded back. Because of this, when using an RIE process in the presence of oxygen, at the above-mentioned power and pressure, the walls 4a and 4b of window 4 are gently sloped. However, when using an RIE process with little oxygen (i.e., less than 10% oxygen) present, edge 3a of photoresist layer 3 is not eroded back. Further, when forming a contact in silicon dioxide layer 2 using an RIE process, the etching is highly anisotropic, etching preferentially in specific directions (i.e., downward) into the substance being etched. In contrast, an isotropic etchant etches in all directions without directional preference. Because the RIE process etches preferentially in a downward direction, walls 2a and 2b of silicon dioxide layer 2 in FIG. 1d are very close to vertical.
The structure illustrated in FIG. 1e exhibits several problems. The electrical connection between portions 5a and 5b of metal layer 5 is extremely thin at corners 5c because of the shadowing caused by wall 2b of silicon dioxide layer 2. In addition, metal layer 5 is also thin at corner 5d because of sharp edge 2d of silicon dioxide layer 2. Because metal layer 5 is so thin at corners 5c and 5d, several problems are known to result. For example, the metal at corners 5c and 5d can act as a fuse when a large current passes through them, thereby creating an open circuit between portion 5a and portion 5b. Furthermore, the metal at corners 5c and 5d can be further weakened and broken due to the effects of corrosion, electron migration, and thermal stress, thus causing a failure. This type of failure may occur some time after fabrication, for example after the device has been included in a larger structure that has been placed into active use.
Although using a reactive ion etch in an oxygen-CHF.sub.3 mixture having a high percentage of oxygen (e.g., greater than 35%) produces sloped walls in silicon dioxide layer 2 (because edge 3a erodes), as the bottom of window 4 approaches layer of silicon substrate 1, it is necessary to reduce the oxygen concentration during the RIE process. This is because a reactive ion etch using a high concentration of CHF.sub.3 will not attack silicon substrate 1 but a reactive ion etch including significant amounts of oxygen will attack silicon substrate 1 rapidly. If an RIE process including oxygen were used past the point at which the profile illustrated in FIG. 1c is achieved, a profile such as the one illustrated in FIG. 2 would result. This profile is utterly unacceptable, since it is extremely difficult to deposit metal layer 5 into window 4 while being able to maintain electrical contact across corner points 6a and 6b. In addition, regions in substrate 1 would be destroyed, potentially destroying devices formed therein.
It is not known how to employ those qualities of an oxygen rich CHF.sub.3 RIE process that cause desirable erosion of photoresist edge 3a and therefore the gently sloped silicon dioxide contact edge 2b without encountering excessive damage to the underlying silicon. Similarly, it is not currently known how to employ those qualities of an oxygen deficient CHF.sub.3 RIE process that cause the etching process to leave exposed silicon essentially undamaged and yet erode the photoresist (and hence etch vertical walls in the silicon dioxode).